How To Use Verilog Instantiation Template

As nosotros saw in a previous article, bigger and circuitous designs are congenital by integrating multiple modules in a hierarchical manner. Modules can be instantiated within other modules and ports of these instances can be connected with other signals within the parent module.

These port connections can be washed via an ordered list or by proper noun.

Port Connection by ordered listing

Ane method of making the connection between the port expressions listed in a module instantiation with the signals inside the parent module is by the ordered list.

mydesign is a module instantiated with the name d0 in some other module chosen tb_top. Ports are connected in a certain lodge which is determined by the position of that port in the port list of the module annunciation. For instance, b in the testbench is connected to y of the pattern simply because both are at the second position in the list of ports.

                      module mydesign ( input  10, y, z,     // ten is at position one, y at 2, 10 at 3 and 	                  output o);          // o is at position iv 	                   	endmodule  	module tb_top; 		wire [one:0]  a; 		wire        b, c; 		 		mydesign d0  (a[0], b, a[1], c);  // a[0] is at position i then it is automatically connected to x 		                                  // b is at position two so it is automatically connected to y 		                                  // a[1] is at position 3 so it is connected to z 		                                  // c is at position four, and hence connexion is with o 	endmodule

Order of ports in the design module should be known for a correct connectedness.

This is very inconvenient because the order might alter if a new port is added to the list or when the number of ports in the design is very large.

Port Connectedness by name

A better way to connect ports is by explicitly linking ports on both the sides using their port name.

The dot . indicates that the port name following the dot belongs to the pattern. The signal name to which the design port has to be continued is given side by side within parentheses ( ).

                      module design_top; 	wire [1:0]  a; 	wire        b, c; 	 	mydesign d0  ( .x (a[0]),    // point "ten" in mydesign should exist continued to "a[0]" in this module (design_top) 	               .y (b),       // signal "y" in mydesign should be continued to "b" in this module (design_top) 	               .z (a[1]),  	               .o (c)); endmodule

It is recommended to code each port connection in a separate line and so that whatsoever compilation mistake message volition correctly point to the line number where the error occured. This is much easier to debug and resolve compared to not knowing which port created the error had they been all in the aforementioned line.

Because these connections are made by proper noun, the order in which they appear is irrelevant. Multiple module example port connections are not allowed.

                      module design_top; 		mydesign d0 ( .x (a[0]), 		              .z (a[1]),     // z at second position is okay because of explicit connection 		              .y (a[1]), 		              .10 (b),        // illegal - x is already connected to a[0] 		              .o (c)); 	endmodule

Unconnected/Floating Ports

Ports that are not connected to any wire in the instantiating module will have a value of high-impedance.

                      module design_top; 	mydesign d0   (              // ten is an input and not connected, hence a[0] will exist Z 	              .y (a[1]), 	              .z (a[1]), 	              .o ());        // o has valid value in mydesign but since 	                             // it is not connected to "c" in design_top, c volition be Z endmodule

Example

Let us have the shift annals example nosotros had seen earlier, and leave some ports unconnected.

                      module shift_reg (   input   d,                     input    clk,                     input   rstn,                     output   q);     wire [2:0] q_net;      dff u0 (.d(d),         .clk(clk), .rstn(rstn), .q(q_net[0]));   dff u1 (.d(q_net[0]), .clk(clk), .rstn(rstn), .q()); 						// Output q is left floating   dff u2 (.d(q_net[1]), .clk(clk), .rstn(rstn), .q()); 						// Output q is left floating   dff u3 (.d(q_net[2]), .clk(clk), .rstn(rstn), .q(q));   endmodule

Note that outputs from instances u1 and u2 are left unconnected in the RTL schematic obtained after synthesis. Since the input d to instances u2 and u3 are now connected to nets that are not being driven by anything it is grounded.

unconnected-port-after-synthesis

In simulations, such unconnected ports will be denoted as high impedance ('hZ) typically shown in waveforms as an orangish line vertically aligned in the middle.

verilog-unconnected-port

All port declarations are implicitly declared equally wire and hence the port direction is sufficient in that case. However output ports that need to store values should be declared as reg data type and can be used in a procedural block similar always and initial merely.

Ports of type input or inout cannot be declared as reg because they are being driven from outside continuously and should not store values, rather reverberate the changes in the external signals as soon equally possible. It is perfectly legal to connect two ports with varying vector sizes, simply the i with lower vector size volition prevail and the remaining $.25 of the other port with a college width will be ignored.

                      // Case #1 : Inputs are by default implicitly declared as blazon "wire" 	module des0_1	(input wire clk ...); 		// wire need not be specified hither 	module des0_2 	(input clk, ...); 			// Past default clk is of type wire 		 	// Case #2 : Inputs cannot be of type reg 	module des1 (input reg clk, ...); 		// Illegal: inputs cannot exist of type reg 	 	// Case #three: Take two modules here with varying port widths 	module des2 (output [3:0] data, ...);	// A module proclamation with four-chip vector equally output 	module des3 (input [7:0] information, ...); 	// A module declaration with viii-scrap vector every bit input 	 	module top ( ... ); 		wire [seven:0] net; 		des2  u0 ( .data(net) ... ); 		// Upper 4-$.25 of net are undriven 		des3  u1 ( .data(net) ... ); 		 	endmodule 	 	// Case #4 : Outputs cannot be connected to reg in parent module 	module top_0 ( ... ); 		reg [3:0] data_reg; 		 		des2 ( .data(data) ...); 	// Illegal: data output port is connected to a reg type signal "data_reg" 	endmodule